Rapid Development of Flexible Validated Processor Models [abstract] (PDF)
David A. Penry, Manish Vachharajani, and David I. August
Proceedings of the Workshop on Modeling, Benchmarking, and Simulation (MoBS), June 2005.
Given the central role of simulation in procesor design and research,
an accurate, validated, and easily modified simulation model is
extremely desirable. Prior work proposed a modeling methodology with
the claim that it allows rapid construction of flexible validated
models. In this paper, we present our experience using this
methodology to construct a flexible validated model of Intel's Itanium
2 processor, lending support to their claims. Our initial model was
constructed by a single researcher in only 11 weeks and predicts
processor cycles-per-instruction(CPI) to within 7.9% on average for
the entire SPEC CINT2000 benchmark suite. We find that aggregate
accuracy for a metric like CPI is not sufficient; aggregate measures
like CPI may conceal remaining internal "offsetting errors" which
can adversely affect conclusions drawn from the model. We then
modified the model to reduce error in specific performance
constituents. In 2 1/2 person-weeks, overall constituent
error was reduced from 3.1% to 2.1%, while simultaneously reducing
average aggregate CPI error to 5.4%, demonstrating that model
flexibility allows rapid improvements to accuracy. Flexibility is
further shown by making significant changes to the model in under
eight person-weeks to explore two novel microarchitectural techniques.