Glossary of Modeling Terms
- Discrete-Event MoC
- A model of concurrency in which components send
data on their output ports. Each time this occurs and event is added
to a time wheel that specifies when the event should arrive. When the
event reaches the head top of the wheel the message is delivered to
the recipient. This is the MoC underlying simulation of VHDL,
Verilog, and SystemC.
- Generics
- A programming language mechanism by which a single piece of code
(function, object, interface, etc.) can manipulate many different
data types without explicitly having a separate entity for each data
type. Templates in C++ are a common example.
- Model of Computation or Model of
Concurrency (MoC)
- The specific semantics of concurrent execution and
composition of components. More information can be found here
- Synchronous Reactive MoC
- A model of concurrency in which components
transitions their outputs in a sequence that conforms to some
predetermined partial order of values. When an output changes value,
the receiving component updates its outputs and the process continues
until the system stabilizes. Esterel
is a language that has a synchronous reactive MoC, as does LSE
- SystemC
- A high-level modeling language based on C++. A subset of SystemC
is synthesizable. More information is available here
- Type Inference
- A mechanism that uses the context of the use of a variable,
object, or component in a language to automatically determine the type
of the entity. This eliminates the need to explicitly declare the
type of every variable.
- Verilog
- A hardware modeling language commonly used for RTL modeling and
synthesis.More information is available here
- VHDL
- A hardware modeling language commonly used for RTL modeling and
synthesis. More information is available here